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625 ksps, 24 - bit, 109 db sigma - delta adc with on - chip buffer data sheet ad7762 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2005C 2014 analog d evices, inc. all rights reserved. technical support www.analog.com features 120 db dynamic range at 78 khz output data rate 109 db dynamic range at 6 25 k hz output data rate 112 db snr at 78 khz output data rate 106 db snr at 6 25 k hz output data rate 625 k hz maximum fully filtered output word rate programmable over - samplin g rate ( 32 to 256 ) fully differential modulator input on - chip differential amplifier for signal buffering low - pass finite impulse respo ns e ( fir ) filter with default or user - programmable coefficients over range alert bit digital offset and gain correction registers filter bypass modes low power and power - down modes synchronization of multiple devices via sync pin applications data acquisition systems vibration analysis i ns trumentation functional block dia gram 05477-001 ad7762 v in+ v in? av dd1 agnd mclk dgnd v drive av dd2 av dd3 av dd4 dv dd decapa/b r bias sync reset db0 to db15 cs drdy rd/wr control logic i/o offset and gain registers diff multibit -? modulator reconstruction v ref+ fir filter engine programmable decimation buf figure 1 . general description the ad7762 is a high performance , 2 4 - bit - analog - to - digital converter (adc). it combines wide input bandwidth and high speed with the benefits of - conversion with a performance of 10 6 db snr at 6 25 k sps , making it ideal for high speed data acquisition. wide dynamic range combined with sign ificantly reduced antialiasing requirement s simplify the design process. an integrated buffer to drive the reference, a differential amplifier for signal buffering and level shifting, an overrange flag, internal ga in and offset registers , and a low - pass d igital fir filter make the ad7762 a compact , highly integrated data acquisition device requiring minimal p eripheral com - ponent selection. in addition , the device offers programmable decimation ra tes , and the digital fir filter can be adjusted if the default characteristics are not a ppropriate to the application. the ad7762 is ideal for applicatio ns demanding high snr without a complex f ront end signal processing design . the differential input is sampled at up to 40 msps by an analog modulator. the modulator output is processed by a series of low - pass filters, the final filter having default or user - programmable coefficients. the sampl e rate, filter corner frequencies , and output word rate are set by a combination of the external clock frequency and the configuration registers of the ad7762 . the reference voltage supplied to t he ad7762 determines the analog input range. with a 4 v reference, the analog input range is 3.2 v differential biased around a common mode of 2 v. this common - mode biasing can be achieved using the on - chip differential amplifier, further reducing the external signal conditioning requirements. the ad7762 is available in an exposed paddle , 64- lead tqfp and is specified over the industria l temperature range from ? 40c to +85c. table 1. related devices part no. description ad776 0 24-b it, 2 .5 m sps, 10 0 db -, parallel interface ad7763 24-b it, 625 ksps, 109 db -, serial interface
important links for the ad7762 * last content update 01/15/2014 02:06 pm similar products & parametric selection tables find similar products by operating parameters documentation an-311: how to reliably protect cmos circuits against power supply overvoltaging an-282: fundamentals of sampled data systems an-342: analog signal-handling for high speed and accuracy an-280: mixed signal circuit technologies an-388: using sigma-delta converters-part 1 an-389: using sigma-delta converters-part 2 an-283: sigma-delta adcs and dacs ms-2210: designing power supplies for high speed adc design tools, models, drivers & software sigma-delta adc tutorial evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad7762 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad7762 data sheet rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications ....................................................................... 5 timing diagrams .......................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 terminolo gy ...................................................................................... 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 13 ad7762 interface ............................................................................ 14 reading data ............................................................................... 14 sharing the p arallel bus ............................................................. 14 writing to the ad7762 .............................................................. 14 reading status and other registers ......................................... 14 clocking the ad7762 ................................................................ 15 example 1 .................................................................................... 15 example 2 .................................................................................... 15 driving t he ad7762 ....................................................................... 16 using the ad7762 ...................................................................... 17 bias resistor selection ............................................................... 17 decoupling and layout recommendations ................................ 18 supply decoupling ..................................................................... 19 additional decoupling .............................................................. 19 reference voltage filtering ....................................................... 19 differential amplifier components ........................................ 19 layout considerations ............................................................... 19 programmable fir filter ............................................................... 20 downloading a user - defined fi lter ............................................ 21 example filter download ......................................................... 21 ad7762 registers ........................................................................... 23 control register 1 reg 0x0001 .............................................. 23 control register 2 addr ess 0x0002 ...................................... 23 status register (read only) ...................................................... 24 offset register address 0x0003 ............................................. 24 gain register address 0x0004 ............................................... 24 overrange register addres s 0x0005 ..................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 1/1 4 rev. 0 to rev. a added exposed pad notation, figure 4 and table 5...7 change to figure 31 20 updated outline dimensions25 8 /05 revis i on 0: initial version
data sheet ad7762 rev. a | page 3 of 28 specificatio ns av dd1 = dv dd = v drive = 2.5 v, av dd2 = av dd3 = av dd4 = 5 v, v ref = 4.096 v, mclk a mplitude = 5 v, t a = 25c, normal mode , using on - chip amplifier with components as shown in tabl e 8 , unless otherwise noted . 1 table 2. parameter test conditio ns /comments specif i cation unit dynamic performance decimate by 256 mclk = 40 mhz, odr = 78 khz, fin = 1 khz dynamic range modulator i nputs shorted 119 120.5 db min db typ signal -to - noise ratio (snr) 2 input a mplitude = ? 0.5 dbfs 112 db typ input a mplitude = ? 60 dbfs 59 db typ spurious - free dynamic range (sfdr) non harmonic, input amplitud e = ? 6 dbfs 126 dbc typ input amplitude = ? 60 dbfs 77 dbc typ total harmonic distortion (thd) input amplitude = ? 0.5 dbf s ? 105 db typ input amplitude = ? 6 d bfs ? 106 db typ input amplitude = ?60 dbfs ? 75 db typ decimate by 64 mclk = 40 mhz, odr = 31 2.5 khz, f in = 1 khz dynamic range modulator i nputs shorted 112 114 db min db typ signal -to - noise ratio (snr) 2 input a mplitude = ? 0.5 dbfs 109.5 db typ spurious - free dynamic range (sfdr) non harmonic, input amplitude = ? 6 dbfs 126 dbc typ decimate by 32 mclk = 40 mhz, odr = 625 khz, fin =100 khz dynamic range modulator inputs shorted 108 109.5 db min db typ signal -to - noise ratio (snr) 2 input a mplitude = ? 0.5 dbfs 107 db typ spurious - free dynamic range (sfdr) n onharmonic, input amplitud e = ? 6 dbfs 120 dbc typ total harmonic distortion (thd) input a mplitude = ? 0.5 dbfs ? 108 db typ input a mplitude = ? 6 dbfs ? 106 db typ dc accuracy resolution 24 bits differential nonlinearity g uaranteed monotonic to 24 bits integral nonlinearity 0.00076 % typ zero error 0.014 % typ 0.02 % max gain error 0.015 % typ zero error drift 0.019 % /c typ gain error drift 0.0002 % /c typ digital filter respo ns e decimate by 32 grou p delay mclk = 40 mhz 47 s typ decimate by 64 group delay mclk = 40 mhz 91.5 s typ decimate by 256 group delay mclk = 40 mhz 358 s typ analog input differential input voltage v in (+) C v in ( ? ), v ref = 2.5 v 2 v p -p v in (+) C v in ( ? ), v ref = 4.096 v 3.25 v p -p input capacitance at internal buffer inputs 5 pf typ at modulator inputs 55 pf typ
ad7762 data sheet rev. a | page 4 of 28 parameter test conditio ns /comments specif i cation unit reference input/output v ref input voltage v dd3 = 3.3 v 5% +2.5 v max v dd3 = 5 v 5% +4.096 v max v ref input dc leakage current 6 a max v ref input capacitance 5 pf max power dissipation total power dissipation normal mode 958 mw max low power mode 661 mw max standby mode clock stopped 6.35 mw max power requir ements av dd1 (modulator supply) 5% +2.5 v av dd2 (general supply) 5% +5 v av dd3 (diff amp supply) +3.15/+5.25 v min/max av dd4 (ref buffer supply) +3.15/+5.25 v min/max dv dd 5% +2.5 v v drive +1.65/+2.7 v min/max normal mode ai dd1 (modulat or) 49/51 ma typ/max ai dd2 (general) 40/42 ma typ/max ai dd4 (reference buffer) av dd4 = 5 v 34/36 ma typ/max low power mode ai dd1 (modulator) 26/28 ma typ/max ai dd2 (general) 20/23 ma typ/max ai dd4 (reference buffer) av dd4 = 5 v 9/10 ma typ/max ai dd3 (diff amp) av dd3 = 5 v, both modes 41/44 ma typ/max di dd both modes 63/70 ma typ/max digital i/o mclk input amplitude 3 5 v typ input capacitance 7.3 pf typ input leakage current 5 a max three - state leakage current (d15: d 0) 5 a max v inh 0.7 v drive v min v inl 0.3 v drive v max v oh 4 1.5 v min v ol 4 0.1 v max 1 see the terminology section. 2 snr specifications in dbs are referred to a full - scale input, fs. tested with an input signal at 0.5 db below full scale, unless otherwise specified. 3 while the ad7762 can function with an mclk amplitude of less than 5 v, this is the recommended amplitude to achieve the performance as stated. 4 tested with a 400 a load current.
data sheet ad7762 rev. a | page 5 of 28 timing specificatio ns av dd1 = dv dd = v drive = 2.5 v, av dd2 = av dd3 = av dd4 = 5 v, t a = 25c, normal mode , unless otherwise noted . table 3. parameter limit at t min , t max unit description f mclk 1 mhz min applied master clock frequency 40 mhz max f iclk 500 khz min internal modulator clock derived fro m mclk 20 mhz max t 1 1 , 2 0.5 t iclk typ drdy pulse width t 2 10 ns min drdy falling edge to cs falling edge t 3 3 ns min rd /wr setup time to cs falling edge t 4 (0.5 t iclk ) + 16 ns max data access time t 5 t iclk min cs low read pulse width t 6 t iclk min cs high pulse width between reads t 7 3 ns min rd /wr hold time to cs rising edge t 8 11 ns max bus relinquish time t 9 4 t iclk min cs low write pulse width t 1 0 4 t iclk min cs high period between address and data t 1 1 5 ns min data setup time t 1 2 0 ns min data hold time 1 t iclk = 1/f iclk . 2 when iclk = mclk, drdy pulse width depends on the mar k/space ratio of applied mclk. timing diagram s data msw lsw + status 05477-002 t 5 t 8 t 7 t 6 t 3 t 4 t 2 t 1 d[0:15] cs rd/wr drdy f igure 2 . parallel interface timing diagram t 9 d[0:15] cs rd/wr t 10 t 11 t 12 register address register data 05477-004 figure 3 . ad7762 register write
ad7762 data sheet rev. a | page 6 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 4. parameters rating av dd1 to gnd ? 0.3 v to + 3 v av dd2 C av dd4 to gnd ? 0.3 v to + 6 v dv dd to gnd ? 0.3 v to + 3 v v drive to gnd ? 0.3 v to + 3 v v in+ , v in C to gnd ? 0.3 v to + 6 v digital input voltage to gnd 1 ? 0.3 v to dv dd + 0.3 v mclk to mclkgnd ? 0.3 v to + 6 v v ref to gnd 2 ? 0.3 v to a v dd4 + 0.3 v agnd to dgnd ? 0.3 v to + 0.3 v input current to any pin except supplies 3 10 ma operating temperature range commercial ? 40c to +85c storage temperature range ? 65c to +150c junction temperature 150c tqfp exposed paddle package ja t hermal impedance 92.7 c/w jc thermal impedance 5.1 c/w lead temperature, soldering vapor phase (60 sec ) 215c infrared (15 sec ) 220c esd 600 v 1 absolute m aximum voltage on digital input s is 3.0 v or dv dd + 0.3 v , whichever is lower. 2 absolute m aximum voltage on v ref input is 6.0 v or av dd4 + 0.3 v , whichever is lower. 3 tra ns ient currents of up to 200 ma do not cause scr latch - up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditio ns above those listed in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditio ns for extended periods may affect devi ce reliability. esd caution
data sheet ad7762 rev. a | page 7 of 28 pin configuration an d fu nction descriptio ns 64 dgnd 63 v drive 62 dgnd 61 db0 60 db1 59 db2 58 db3 57 db4 56 db5 55 db6 54 db7 53 dgnd 52 db8 51 db9 50 db10 49 db 1 1 47 db13 46 db14 45 db15 42 dgnd 43 dgnd 44 v drive 48 db12 notes 1. connect the exposed p ad t o agndx with six t o eight vias. 41 dv dd 40 cs 39 rd/wr 37 reset 36 sync 35 dgnd 34 agnd1 33 a v dd1 38 drdy 2 mclkgnd 3 mclk 4 a v dd2 7 agnd1 6 a v dd1 5 agnd2 1 dgnd 8 deca p a 9 refgnd 10 v ref+ 12 a v dd4 13 agnd2 14 a v dd2 15 a v dd2 16 agnd2 1 1 agnd4 pin 1 17 r bias 18 agnd2 19 v in a+ 20 v in a? 21 v out a? 22 v out a+ 23 agnd3 24 a v dd3 25 v in + 26 v in ? 27 a v dd2 28 agnd2 29 agnd3 30 decapb 31 agnd3 32 agnd3 ad7762 t o p view (not to scale) 05477-005 figure 4 . 64 - lead tqfp pin configuration table 5 . pin function descriptio ns pin no. mnemonic description 6, 33 av dd1 2.5 v power supply for modulator . these pi ns should be decoupled to agnd 1 with 100 nf and 10 f capacitors on each pin. 4, 14, 15, 27 av dd2 5 v power supply. these pi ns should be decoupled to agnd 2 with 100 nf capacitors on each of pin 4, pin 14 , and pin 15. pin 27 should be connected to p in 14 via a 15 nh inductor. 24 av dd3 3.3 v to 5 v power supply for differential amplifier. these pi ns should be decoupled to agnd 3 with a 100 nf capacitor. 12 av dd4 3.3 v to 5 v power supply for reference buffer . this pin should be decoupled to agnd 4 with a 10 nf capacitor in series with a 10 ? resistor. 7, 34 agnd1 power supply ground for analog circuitry p owered by a v dd1 . 5, 13, 16, 18, 28 agnd2 power supply ground for analog circuitry p owered by a v dd2 . 23, 29, 31, 32 agnd3 power supply ground for analog circuitry p owered by a v dd3 . 11 agn d4 power supply ground for analog circuitry p owered by a v dd4 . 9 refgnd reference ground. ground connection for the reference voltage. 41 dv dd 2.5 v power supply for digital circuitry and fir filter . this pin should be decoupled to dgnd with a 100 nf cap acitor. 44, 63 v drive logic power supply input, 1.8 v to 2.5 v. the voltage supplied at these pi ns determine s the operating voltage of the logic interface. both these pi ns must be connected together and tied to the same supply. each pin should also be dec oupled to dgnd with a100 nf capacitor. 1, 35, 42, 43, 53, 62, 64 dgnd ground reference for digital circuitry. 19 v in a+ positive input to differential amplifier. 20 v in a ? negative input to differential amplifier. 21 v out a ? negative output from differen tial amplifier. 22 v out a+ positive output from differential amplifier. 25 v in + positive input to the modulator. 26 v in ? negative input to the modulator.
ad7762 data sheet rev. a | page 8 of 28 pin no. mnemonic description 10 v ref+ reference input. the input range of this pin is determined b y the reference buffer supply voltage (av dd4 ). see the reference voltage filtering s ection for more details. 8 decap a decoupling pin. a 100 nf capacitor must be i ns erted between this pin and agnd 1. 30 decapb decoupling pin. a 33 pf capacitor must be inse rted between this pin and agnd3. 17 r bias bias current setting pin . a resistor must be i ns erted between this pin and agnd 1 . for more details , see the bias resistor selection s ection. 45 to 52, 54 to 61 db15 to db 8 db7 to db0 16- bit bidirectional data bus . these are three - state pi ns that are controlled by the cs pin and the rd /wr pin . the operating voltage for these pi ns is determined by the v drive voltage. see the ad7762 interface s ection for more details. 37 reset a falling edge on this pin resets all internal digital circuitry and powers down the part. holding this pin low keeps the ad 7762 in a reset state. 3 mclk master clock input. a low jitter digital clock must be applied to this pin. the output data rate depends on the frequency of this clock. see the section clocking the ad7762 for more details. 2 mclkgnd ma ster clock ground se ns ing pin . 36 sync synchronization input. a falling edge on this pin resets the internal filter. this can be used to synchronize multiple devices in a system. 39 rd /wr read/write input. this pin, in conjunction with the chip se lect pin, is used to read and write data to and from the ad7762 . if this pin is low when cs is low, a read takes place. if this pin is high and cs is low, a write occurs. see the ad7762 interface s ection for more details. 38 drdy data ready output. each time that new conversion data is available, an active low pulse, ? iclk period wide, is produced on this pin. see the ad7762 interface s ection for more details. 40 cs chip select input. used in conjunction with the rd /wr pin to read and write data to and from the ad7762 . see the ad7762 interface s ection for more details. epad exposed pad. connect the exposed pad to agndx with six to eight vias.
data sheet ad7762 rev. a | page 9 of 28 terminology signal -to - noise ratio (snr) snr is th e ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) the ratio of the rms su m of harmonics to the fundamental. for the ad7762 , it is defined as ( ) 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 db + + + + = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 ,. and v 6 are the rms amplitudes of the second to the sixth harmonics. non h armonic spurious - free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component , excluding harmonics. dynamic range dynamic r ange is the ratio of the rms value o f the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. integral nonlinearity (inl) the maximum deviation from a straight line passing through the endpoints of the adc tra ns fer fun ction. differential nonlinearity (dnl) the difference between the measured and t he ideal 1 - lsb change between any two adjacent codes in the adc. zero error the zero error is the difference between the ideal midscale input voltage (0 v) and the actual volta ge producing the midscale output code. zero error drift the change in the actual zero error value due to a temperature change of 1c. it is expressed as a percentage of the zero error at room temperature. gain error the first tra ns ition (from 100000 to 10 0001) should occur for an analog voltage 1/2 lsb above the nominal negative full scale. the last tra ns ition (from 011110 to 011111) should occur for an analog voltage 1 1/2 lsb below the nominal full scale. the gain error is the deviation of the differe nce between the actual level of the last tra ns ition and the actual level of the first tra ns ition , from the difference between the ideal levels. gain error drift the change in the actual gain error value due to a temperature change of 1c. it is expressed a s a percentage of the gain error at room temperature.
ad7762 data sheet rev. a | page 10 of 28 typical performance characteristics av dd1 = dv dd = v drive = 2.5 v, av dd2 = av dd3 = av dd4 = 5 v, v re f = 4.096 v, t a = 25c, normal mode , unless otherwise noted. all ffts are generated from 65 , 536 sam ples using a 7 - term blackman - harris window. 0 4000 8000 12000 16000 20000 ? 200 0 ? 25 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 24000 frequency (hz) amplitude (db) 05477-006 figure 5 . normal mode fft, 1 khz, ? 0.5 db input tone, 256 decimation 0 4000 8000 12000 16000 20000 ? 200 0 ? 25 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 24000 frequency (hz) amplitude (db) 05477-007 figure 6 . normal mode fft, 1 khz, ? 6 db input tone, 256 decimation 0 4000 8000 12000 16000 20000 ? 200 0 ? 25 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 24000 frequency (hz) amplitude (db) 05477-008 figure 7 . normal mode fft, 1 khz, ? 60 db input tone, 256 decimation 0 4000 8000 12000 16000 20000 ? 200 0 ? 25 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 24000 frequency (hz) amplitude (db) 05477-009 figure 8 . low power fft, 1 khz, ? 0.5 db input tone, 256 decimation 0 4000 8000 12000 16000 20000 ? 200 0 ? 25 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 24000 frequency (hz) amplitude (db) 05477-010 figure 9 . low power fft, 1 khz, ? 6 db input tone, 256 decimation 0 4000 8000 12000 16000 20000 ? 200 0 ? 25 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 24000 frequency (hz) amplitude (db) 05477-011 figure 10 . low power fft, 1 khz, ?60 db input tone, 256 decimation
data sheet ad7762 rev. a | page 11 of 28 05477-060 frequency (hz) amplitude (db) ? 25 0 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 ? 200 60000 0 120000 180000 240000 300000 figure 11. normal mode fft , 100 khz, ?0.5 db input tone, 32 decimation 05477-061 frequency (hz) amplitude (db) ? 25 0 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 ? 200 60000 0 120000 180000 240000 300000 figure 12. normal mode fft, 100 khz, ? 6 db input tone, 32 decimation 05477-062 decimation rate (x) snr (dbfs) 120 106 0 256 118 116 114 112 110 108 64 128 192 ? 0.5db ? 60db ? 6db figure 13. n ormal mode snr vs. decimation rate, 1 khz input tone 05477-063 frequency (hz) amplitude (db) ? 25 0 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 ? 200 60000 0 120000 180000 240000 300000 figure 14. low power fft, 100 khz, ? 0.5 db input tone, 32 decimation 05477-064 frequency (hz) amplitude (db) ? 25 0 ? 50 ? 75 ? 100 ? 125 ? 150 ? 175 ? 200 60000 0 120000 180000 240000 300000 figure 15. low power fft, 100 khz, ? 6 db input tone, 32 decimation 05477-065 decimation rate (x) snr (dbfs) 116 104 0 256 64 128 192 112 108 ? 60db ? 0.5db ? 6db figure 16. low power snr vs. decimation rate, 1 khz input tone
ad7762 data sheet rev. a | page 12 of 28 4500 0 8385222 05477-055 24-bit code occurrence 4000 3500 3000 2500 2000 1500 1000 500 8385238 8385254 8385270 figure 17. normal mode, 24 - bit histogram, 256 decimation 0.0010 ? 0.0010 0 16777216 05477-056 24-bit code inl (%) 0.0005 0 ? 0.0005 4194304 8388608 12582912 +25 c ? 40 c +85 c figure 18 . 24 - bit inl, normal mode 0.6 ?0.6 0 16777216 05477-057 24-bit code dnl (lsb) 4194304 8388608 12582912 0.4 0.2 0 ?0.2 ?0.4 figur e 19. 24 - bit dnl 3000 0 8383530 05477-058 24-bit code occurrence 2500 2000 1500 1000 500 83835246 8383562 8383578 8383594 8383610 figure 20. low power, 24 - bit histogram, 256 decimation 0.0015 ? 0.0010 0 16777216 05477-059 24-bit code inl (%) 0.0005 0.0010 0 ? 0.0005 4194304 8388608 12582912 +25 c ? 40 c +85 c figure 21 . 24 - bit inl, low power mode
data sheet ad7762 rev. a | page 13 of 28 theory of operation the ad7762 employs a - conversion technique to convert the analog input into an equivalent digital word. the modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate equal to iclk . due to the high ov er sampling rate, that spreads the quantization noise from 0 to f iclk , the noise energy contained in the band of interest is reduced ( figure 22 a). to further reduce the quantization noise, a high order mo dulator is employed to shape the noise spectrum; so that most of the noise energy is shifted out of the band of interest ( figure 22 b). the digital filtering that follows the modulator removes the large out - of - band quantization noi se ( figure 22 c ) while also reducing the data rate from f iclk at the input of the filter to f iclk /8 or less at the output of the filter, depending on the decimation rate used. digital filtering has certain advantages over analog f iltering. it does not introduce significant noise or distortion and can be made perfectly linear phase. the ad7762 employs three f ir filters in series. by using different combinatio ns of decimati on ratios and filter selection and bypassing, data can be obtained from the ad7762 at a l arge range of data rates. the first filter receives data from the modulator at iclk mhz where it is decima ted by four to output data at iclk/4 mhz. this partially filtered data can also be output at this stage. the second filter allows the decimation rate to be chosen from 4 to 32 . the third filter has a fixed decimation rate of 2 , is user programmable , and has a default configuration. it is described in detail in the programmable fir filter s ection. this filter can be bypassed. table 6 lists some characteristics of the default filter. the group delay of the filter is defined to be the delay to the cent er of the impulse respo ns e and is equal to the computation + filter delays. the delay until valid data is available (the dvalid status bit is set) is equal to 2 the filter delay + the comput ation delay. 04975-037 quantization noise f iclk \2 band of interest a. f iclk \2 noise shaping band of interest b. f iclk \2 band of interest digital filter cutoff frequency c. figure 22 . - adc table 6 . configuration w ith default filter icl frequency filter 1 filter 2 filter 3 data state computation delay filter delay pass - b and bandwidth utput data rate (dr) 20 mhz 4 4 2 fully f iltered 1.775 s 44.4 s 250 khz 625 khz 20 mhz 4 8 bypassed partially filtered 2.6 s 10.8 s 140.625 khz 625 khz 20 mhz 4 8 2 fully filtered 2.25 s 87.6 s 125 khz 312.5 khz 20 mhz 4 16 bypassed partially filtered 4.175 s 20.4 s 70.3125 khz 312.5 khz 20 mhz 4 16 2 fully filtered 3.1 s 174 s 62.5 khz 156.25 khz 20 mhz 4 32 bypassed partially filtered 7.325 s 39.6 s 35.156 khz 156.25 khz 20 mhz 4 32 2 fully filtered 4.65 s 346.8 s 31.25 khz 78.125 khz 12.288 mhz 4 8 2 fully filtered 3.66 s 142.6 s 76.8 khz 192 khz 12.288 mhz 4 16 2 fully filtered 5.05 s 283.2 s 38.4 khz 96 khz 12.288 mhz 4 32 bypassed partially filtered 11.92 s 64.45 s 21.6 khz 96 khz 12.288 mhz 4 32 2 fully filtered 7.57 s 564.5 s 19.2 khz 48 khz
ad7762 data sheet rev. a | page 14 of 28 ad7762 interface reading data the ad7762 uses a 16-bit bidirectional parallel interface. this interface is controlled by the rd /wr and cs pins. when a new conversion result is available, an active low pulse is output on the drdy pin. to read a conversion result from the ad7762 , two 16-bit read operations are performed. the drdy pulse indicates that a new conversion result is available. both rd /wr and cs go low to perform the first read operation. shortly after both these lines go low, the data bus becomes active and the 16 most significant bits (msbs) of the conversion result are output. the rd /wr and cs lines must return high for a full iclk period before the second read is performed. this second read contains the 8 least significant bits (lsbs) of the conversion result along with 6 status bits. these status bits are shown in table 7. descriptions of the other status bits are in table 15. table 7. status bits during data read d7 d0 dvalid ovr ufilt lpwr filtok dlok 0 0 shortly after rd /wr and cs return high, the data bus returns to a high impedance state. both read operations must be completed before a new conversion result is available because the new result overwrites the contents on the output register. if a drdy pulse occurs during a read operation, the data read is invalid. sharing the parallel bus by its nature, the high accuracy of the ad7762 makes it sensitive to external noise sources. these include digital activity on the parallel bus. for this reason, it is recommended that the ad7762 data lines are isolated from the system data bus by means of a latch or buffer to ensure that there is no digital activity on the d0 to d15 pins that is not controlled by the ad7762 . if multiple, synchronized ad7762 parts that share a properly distributed common mclk signal exist in a system, these parts can share a common bus without being isolated from each other. this bus can then be isolated from the system bus by a single latch or buffer. writing to the ad7762 while the ad7762 is configured to convert analog signals with the default settings on reset, there are many features and parameters on this part that the user can change by writing to the device. because some of the programmable registers are 16 bits wide, two write operations are required to program a register. the first write contains the register address while the second write contains the register data. an exception is when a user filter is being downloaded to the ad7762 . this is described in detail in the downloading a user-defined filter section. the ad7762 registers section contains the register addresses and more details. figure 3 shows a write operation to the ad7762 . the rd /wr line is held high while the cs line is brought low for a minimum of 4 iclk periods. the register address is latched during this period. the cs line is brought high again for a minimum of 4 iclk periods before the register data is put onto the data bus. if a read operation occurs between the writing of the register address and the register data, the register address is cleared and the next write must be the register address again. this also provides a method to get back to a known situation if the user forgets whether the next write is an address or data. generally, the ad7762 is written to and configured on power- up and very infrequently, if at all, after that. following any write operation, the full group delay of the filter must pass before valid data is output from the ad7762. reading status and other registers the ad7762 features a number of programmable registers. to read back the contents of these registers or the status register, the user must first write to the control register of the device, setting a bit corresponding to the register to be read. the next read operation outputs the contents of the selected register instead of a conversion result. the ad7762 registers section provides more information on the relevant bits in the control register.
data sheet ad7762 rev. a | page 15 of 28 clocking the ad7762 the ad7762 requires an external low jitter clock source. this signal is applied to the mclk pin , and the mclkgnd pin is used to se ns e the ground from the clock source. an internal cl ock signal (iclk) is derived from the mclk input signal. the iclk controls the internal operation s of the ad7762 . the maximum iclk frequency is 20 mhz , but due to an internal clock divider, a ra nge of mclk frequencies can be used. there are two ways to generate the iclk: iclk = mclk ( cdiv = 1) i clk = mclk / 2 ( cdiv = 0) these optio ns are selected from the control register ( s ee the ad7762 r egisters s ection for more details). on power - up, the default is iclk = mclk/ 2 to e ns ure that the part can handle the maximum mclk frequency of 40 mhz. for output data rates equal to those used in audio systems, a 12.288 mhz iclk frequency can be used. as shown in table 6 , output data rates of 192 khz , 96 khz, and 48 khz are achievable with this iclk frequency. as mentioned previously, this iclk frequency can be derived from different mclk frequencies. the mclk jitter requirements depend on a number of factors and are given by 20 ) db ( ) ( 10 2 snr in rms j f osr t r = where: osr = over - sampling ratio = odr f iclk f in = maximum input frequency snr (db) = target snr example 1 this example can be taken from table 6 , where: odr = 6 25 k hz f iclk = 20 mhz f in (max) = 250 k hz snr = 108 db ps 6 . 3 10 10 250 2 32 6 3 ) ( = r = rms j t this is the maximum allowable clock jitter for a full - scale , 250 k hz input tone with the given iclk and output data rate . example 2 ta k e a second example fro m table 6 , where : odr = 48 khz f iclk = 12.288 mhz f in (max) = 19.2 khz snr = 120 db ps 133 10 10 2 . 19 2 256 6 3 ) ( = r = rms j t the input amplitude also has an effect on these jitter figures. if, for example, the input level was 3 db below full sc ale, the allowable jitter would be increased by a factor of 2 , increasing the first example to 2.53 ps rms . this happe ns when the maximum slew rate is decreased by a reduction in amplitude. figure 23 and fi gure 24 illustrate this point , showing the maximum slew rate of a sine wave of the same frequency but with different amplitudes. 1 ?1.0 04975-038 0.5 0 ?0.5 figure 23 . maximum slew rate of sine wave with amplitude of 2 v p - p 1 ?1.0 04975-039 0.5 0 ?0.5 figure 24 . maximum slew rate of same frequency sine wave with amplitude of 1 v p - p
ad7762 data sheet rev. a | page 16 of 28 driving the ad7762 the ad7762 has an on-chip differential amplifier that operates with a supply voltage (av dd3 ) from 3.15 v to 5.25 v. for a 4.096 v reference, the supply voltage must be 5 v. to achieve the specified performance in normal mode, the differential amplifier should be configured as a first-order antialias filter, as shown in figure 25. any additional filtering should be carried out in previous stages using low noise, high performance op amps, such as the ad8021. suitable component values for the first-order filter are listed in table 8. the values in table 8 yield a 10 db attenuation at the first alias point of 19 mhz. 04975-040 a1 r in r fb c fb r in r m r m c s r fb c fb v in ? a b v in + figure 25. differential amplifier configuration table 8. normal mode component values v ref r in r fb r m c s c fb 4.096 v 1 k 655 18 5.6 pf 33 pf figure 26 shows the signal conditioning that occurs using the circuit in figure 25 with a 2.5 v input signal biased around ground and having the component values and conditions in table 8. the differential amplifier always biases the output signal to sit on the optimum common mode of v ref /2, in this case 2.048 v. the signal is also scaled to give the maximum allowable voltage swing with this reference value. this is calculated as 80% of v ref , that is, 0.8 4.096 v 3.275 v p-p on each input. to obtain maximum performance from the ad7762 , it is advisable to drive the adc with differential signals. figure 27 shows how a bipolar, single-ended signal biased around ground can drive the ad7762 with the use of an external op amp, such as the ad8021. with a 4.096 v reference, a 5 v supply must be provided to the reference buffer (av dd4 ). with a 2.5 v reference, a 3.3 v supply must be provided to av dd4 . 04975-041 + 2.5 v 0v ? 2.5v + 2.5 v 0v ? 2.5v +3.685v +2.048v +0.410v +3.685v +2.048v +0.410v a v in + v in ? b figure 26. differential amplifier signal conditioning 04975-042 a1 r in r fb c fb r in r m r m c s r fb c fb v in ? v in v in + ad8021 2r 2r r figure 27. single-ended-t o-differential conversion 05477-043 cs2 cpb2 ss4 sh4 cpa ss2 sh2 cs1 cpb1 ss3 sh3 ss1 sh1 analog modulator v in + figure 28. equivalent input circuit the ad7762 employs a double sampling front end, as shown in figure 28. for simplicity, only the equivalent input circuit for v in + is shown. the equivalent input circuitry for v in ? is the same.
data sheet ad7762 rev. a | page 17 of 28 the sampling switches ss1 and ss3 are driven by iclk, whereas the sampling switches ss2 and ss4 are driven by iclk . when iclk is high, the analog input voltage is connected to cs1. on the falling edge of iclk, the ss1 and ss3 switches open , and the analog input is sampled on cs1. similarly, when iclk is low, the analog input voltage is connected to cs2. on the rising edge of iclk, the ss2 and ss4 switches open, and the analog input is sampled on cs2. capacitors cp a , cp b 1 , and cp b 2 represent parasitic capacitances that include the junction capacitances associated with the mos switches. table 9. equivalent component values mode cs1 cs2 c p a cpb1/2 normal 51 pf 51 pf 12 pf 20 pf low power 13 pf 13 pf 12 pf 5 pf using t he ad7762 the following is the recommended sequence for powering up and using the ad7762 . 1. apply p ower . 2. start the clock oscillator, applying mclk . 3. ta ke reset low for a minimum of 1 mclk cycle . 4. wait a minimum of 2 mclk cycles after reset has been released. 5. write to control register 2 to power up the adc and the differential amplifier as required. the correct clock divider ( cdiv ) ratio should be programmed now . 6. write to control register 1 to set the output data rate . 7. wait a minimum of 5 mclk cycles after cs has been released. 8. ta ke sync low for a minimum of 4 mclk cycles , if required , to synchronize multiple parts. data can then be read from the part using the default filter, offset, gain , and over range threshold values. the conversion data read is not valid , however , until the group delay of the filter has passed. when this has occurred, the dvalid bit read with the data lsw is set , indicating that the data is indeed valid. the user can then download a different filter , if required (see downloading a user - def ined filter ). values for gain, offset , and over range threshold registers can be written or read at this stage. bias resistor select ion the ad7762 requires a resistor to be connected between the r bias pin and agnd 1 . the value for this resistor is dependant on the reference voltage being applied to the device. the resistor value should be selected to give a current of 25 a through the resistor to ground. for a 2.5 v reference voltage, the correct resistor value is 100 k ? and for a 4.096 v reference, the correct resistor value is 1 60 k ? .
ad7762 data sheet rev. a | page 18 of 28 decoupling and layout recommendations due to the high performance nature of the ad7762 , correct decoupling and layout techniques are required to obtain the performance as stated within this datasheet. figure 29 shows a simplified connection diagram for the ad7762. v in a+ v in a? v out a? v out a+ ina+ ina? outa? outa+ decapa decapb v in + v in ? v ref + vin+ vin? vref refgnd r bias dgnd dgnd dgnd dgnd dgnd dgnd dgnd 19 20 21 22 8 30 25 26 10 9 17 1 35 42 43 53 62 64 db0 db2 db1 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db0 db2 db1 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 cs rd/wr reset sync drdy mclk mclkgnd cs rd/wr reset sync drdy mclk agnd1 agnd1 agnd2 agnd2 agnd2 agnd2 agnd2 agnd3 agnd3 agnd3 agnd3 agnd4 7 34 5 13 16 18 28 23 29 31 32 11 av dd2 av dd2 av dd2 av dd4 av dd1 av dd1 av dd3 av dd2 v drive v drive dv dd pin 1 4 pin 1 5 pin 4 pin 12 pin 6 pin 3 3 pin 2 4 pin 2 7 pin 4 4 pin 6 3 pin 41 14 15 4 12 6 33 24 27 44 63 41 ad7762bsv 61 60 59 58 55 54 50 49 46 45 40 37 36 38 3 2 57 56 52 51 48 47 39 r19 160k ? c64 33pf c7 100nf db (0:15) u2 av dd3 pin 24 (vdif1) c54 100nf l6 dv dd pin 41 (dvdd) c58 100nf l8 av dd2 pin 4 (rhs) c48 100nf l1 pin 15 (vbias) c50 100nf l3 pin 14 (lhs) pin 27 c62 100nf l2 l9 av dd4 pin 12 (vbuf) c59 10nf l4 r38 10 ? av dd1 pin 5 (vmod1) c52 100nf l5 pin 33 (vmod2) c53 100nf l11 v drive pin 44 (vdrv1) c56 100nf l7 pin 63 (vdrv2) c57 100nf l12 05477-046 figure 29. simplified connection diagram
data sheet ad7762 rev. a | page 19 of 28 supply decoupling every supply pin must be connected to the appropriate supply via a ferrite bead and decoupled to the correct ground pin with a 100 nf , 0603 case size, x7r dielectric capacitor. there are two exceptions to this: ? pin 12 (a v dd4 ) must have a 10 resistor inserted between the pin and a 10 nf decoupling capacitor. ? pin 27 (av dd 2 ) does not require a separate decoupling capacitor or a direct connection to the supply , but instead is connected to pin 14 via a 15 nh inductor. additional decouplin g there are two other decoupling pins on the ad7762 pin 8 (decapa) and pin 30 (decapb). pin 8 should be decoupled with a 100 nf capacitor , and pin 30 re quires a 33 pf capacitor. reference voltage fi ltering a low noise reference source , such as the adr431 (2.5 v) or adr434 (4.096 v) , is suitable for use with the ad7762 . the reference voltage supplied to the ad7762 should be decoupled and filtered , as shown in figure 30. the recommended scheme for the reference voltage supply is a 100 series resistor connected to a 100 f tantalum capacitor, followed by series resistor of 10 , and finally a 10 nf decoupling capacitor very close to the v ref + pin . 04975-047 +12v pin10 vout 2 +vin 6 4 c15 10f c9 100nf c10 100nf r30 100w r17 10w + c46 10nf c11 100f + adr434 gnd u3 figure 30 . reference connection differential amplifi er comp onents the correct components for use around the on - chip differential amplifier are detailed in table 8 . matching the components on both sides of the differential amplifier is important to minimize distortion of the signal applied to the amplifier. a tolerance of 0.1% or better is required for these components. symmetrical routing of the tracks on both sides of the differential amplifier also assist s in achieving stated performance. layout consideration s while using the correct comp onents is essential to achieve optimum performance, the correct layout is just as important. the design tools section of the ad7762 product page on the analog devices website contains the gerber files for the ad7762 evaluation board . these files should be used as a reference when designing a ny system using the ad7762 . the loca tion and orientation of some of the components mentioned in previous sections is critical , and particular attention must be paid to the components which are located close to the ad7762 . locating these components further away from the devices can have a direct impact on the maximum performance achievable. the use of ground planes also should be carefully considered. to ensure that the return currents through the decoupling capacitors are flowing to the correct ground pin, the ground side of the capacitors should be as close to the g r ound pin associated with that supply. a ground plane should not be relied on as the sole return path for decoupling capacitors because the return current path using grou nd planes is not easily predictable .
ad7762 data sheet rev. a | page 20 of 28 programmable fir fil ter as previously mentioned, the third fir filter on the ad7762 is user programmable. the default coefficients that are loaded on r eset are given in table 10 and the frequency respo ns e s are shown in figure 31. the frequencies quoted in figure 31 scale directly with the output data rate . table 10 . default filter coefficients no. dec. value hex value no. dec. value hex value 0 53656736 332bca0 24 700847 ab1af 1 25142688 17fa5a0 25 ?70922 401150a 2 ?4497814 444a196 26 ? 583959 408e917 3 ?11935847 4b62067 27 ?175934 402af3e 4 ?1313841 4140c31 28 388667 5ee3b 5 6976334 6a734e 29 294000 47c70 6 3268059 31dddb 30 ?183250 402cbd2 7 ?3794610 439e6b2 31 ?302597 4049e05 8 ?3747402 4392 e4a 32 16034 3ea2 9 1509849 1709d9 33 238315 3a2eb 10 3428088 344ef8 34 88266 158ca 11 80255 1397f 35 ?143205 4022f65 12 ?2672124 428c5fc 36 ?128919 401f797 13 ?1056628 4101f74 37 51794 ca52 14 1741563 1a92fb 38 121875 1dc13 15 1502200 16ebf8 39 16426 402a 16 ?835960 40cc178 40 ?90524 401619c 17 ?1528400 4175250 41 ? 63899 400f99b 18 93626 16dba 42 45234 b0b2 19 1269502 135efe 43 114720 1c020 20 411245 6466d 44 102357 18fd5 21 ?864038 40d2f26 45 52669 cdbd 22 ?664622 40a242e 46 15559 3cc7 23 434489 6a139 47 1963 7ab the default filter should be sufficient for almost all applicatio ns . it is a standard brick wall filter with a symmetrical impulse respo ns e. the default filter has a length of 96 taps in non - aliasing with 120 db of attenuation at nyquist. this filter not only performs signal antialiasing, but also suppresses out - of - band quantization noise produced by the analog - to - digital conversion process. any significant relaxation in the stop - band attenuation or tra ns ition bandwidth relative to the default filter can result in a failure to meet the snr specificatio ns . to create a filter, note the following: ? the filter must be even, symmetrical fir. ? the coefficients are in sign - and - magnitude format with 26 magnitude bits and sign coded as pos itive = 0. ? the filter length must be between 12 taps and 96 taps in steps of 12. ? because the filter is symmetrical, the number of coefficients that must be downloaded is half the filter length. the default filter coefficients exemplify this with only 48 c oefficients listed for a 96 - tap filter. ? coefficients are written from the center of impulse respo ns e (adjacent to the point of symmetry) outwards. ? the coefficients are scaled so that the in - band gain of the filter is equal to 134217726 with the coefficien ts rounded to the nearest integer. for a low - pass filter, this is the equivalent of having the coefficients sum arithmetically (including sign) to a 67108863 (0x3ff ffff) posit ive value over the half - impulse respo ns e coefficient set (max imum 48 coefficien ts). any deviation from this introduces a gain error. ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 100 400 500 300 200 600 frequency (khz) amplitude (db) 0 05477-044 ?0.1db frequency = 251khz pass-band ripple = 0.05db stop band = 312.5khz ?3db frequency = 265khz figure 31 . default filter frequency respo ns e (62 5 k hz odr) the procedure for downloading a user - defined filter is detailed in the downloading a user - de fined filter section.
data sheet ad7762 rev. a | page 21 of 28 downloading a user - defined filter as previously mentioned, the filter coefficients are 27 bits in length; 1 sign and 26 magnitude bits. because the ad7762 has a 16 - bit parallel bus, the coefficients are padded with 5 msb 0s to generate a 32 - bit word and split into two 16 - bit words for downloading. the first 16 - bit word for each coefficient becomes (00000, sign bit, magnitude [25:16]), while the second word becomes (mag nitude [15:0]). to e ns ure that a filter is down - loaded correctly, a checksum must also be generated and then downloaded following the final coefficient. the checksum is a 16 - bit word generate d by splitting each 32 - bit word into 4 bytes and summing all by tes from all coefficients up to a maximum of 192 bytes (48 coefficients 4 bytes). the same checksum is generated internally in the ad7762 and compared with the checksum downloaded. the dl_ok bi t in the status register is set if these two checksums agree. t o download a user filter: 1. write to control register 1 , setting the dl_filt bit and also the correct filter length bits corresponding to the length of the filter to be downloaded ( s ee tabl e 11). 2. write the first half of the current coefficient data (00000, sign bit, magnitude [25:16]). the first coefficient to be written must be the one adjacent to the point of filter symmetry. 3. write the second half of the current coeff icient data (magnitude [15:0]). 4. repeat step 2 and step 3 for each coefficient. 5. write the 16 - bit checksum. 6. use these methods to verify that the filter coefficients are downloaded correctly: a. read the status register, checking the dl_ok bit. b. read data and obs erve the status of the dl_ok bit. note that because the user coefficients are stored in ram, they are cleared after a reset operation or a loss of power. table 11 . filter length values flen[3:0] n umber of coefficie nts filter length 0000 default default 0001 6 12 0011 12 24 0101 18 36 0111 24 48 1001 30 60 1011 36 72 1101 42 84 1111 48 96 example filter downl oad the following is an exam ple of downloading a short user - defined filter with 24 taps. the freque ncy respo ns e is shown in figure 32. 10 ? 80 0 600 04975-045 frequency (khz) amplitude (db) 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 100 200 300 400 500 figure 32 . 24 - tap fir frequency respo ns e the coefficients for the filter are listed in table 12 and are shown from the center of symmetry outw ards. the raw coefficients were generated using a commercia l filter design tool and scaled app ropriately so their sum equals 67108863 (0x3ff ffff). table 12 . 24 - tap fir coefficients coefficient raw scaled 1 0.365481974 53188232 2 0.201339905 29300796 3 0.009636604 1402406 4 ? 0.075708848 ? 11017834 5 ? 0.042856209 ? 6236822 6 0.019944246 2902466 7 0.036437914 5302774 8 0.007592007 1104856 9 ? 0.021556583 ? 3137108 10 ? 0.024888355 ? 3621978 11 ? 0.012379538 ? 1801582 12 ? 0.001905756 ? 277343
ad7762 data sheet rev. a | page 22 of 28 table 13 shows the h ex values (in sign and magnitude format) that are downloaded to the ad7762 to realize this filter. the table is also split into the byte s that are all summed to produce the checksum. the checksum generated from these coefficients is 0x0e6b. table 13 . filter hex values word 1 word 2 coefficient byte 1 byte 2 byte 3 byte 4 1 03 2b 96 88 2 01 bf 18 3c 3 00 15 66 26 4 04 a8 1e 6a 5 04 5f 2a 96 6 00 2c 49 c2 7 00 50 e9 f6 8 00 10 db d8 9 04 2f de 54 10 04 37 44 5a 11 04 1b 7d 6e 12 04 04 3b 5f table 14 lists the 16- bit words the user would write to the ad7762 to set up the adc and download this filter , assuming an output data rate of 625 k hz has already been selected. table 14. word description 0x0001 address of control register 1. 0x8079 cont rol register data. dl filter, set filter length = 24, set output data rate = 625 k hz. 0x032b first coefficient, word 1. 0x9688 first coefficient, word 2. 0x01bf second coefficient, word 1. 0x183c second coefficient, word 2. other coefficients . 0x0404 twelfth (final) coefficient, word 1. 0x3b5f final coefficient, word 2. 0x0e6b checksum. wait (0.5 t iclk number of unused coefficients) f or ad7762 to fill remaining unused coefficient s with 0s. 0x0001 address of control register. 0x0879 control register data. set read status and maintain filter length and decimation settings. read contents of status register. check bit 7 (dl_ok) to determine that the filter was downloaded correctly.
data sheet ad7762 rev. a | page 23 of 28 ad 7762 registers the ad7762 has a number of user - programmable registers. the control registers are used to set the decimation rate, the filter configuration, the clock divider , and so on . there are also digital gain, offset , and overrange threshold registers. writing to these registers involves writing the register ad dress first, then a 16 - bit data - word. register a ddresses, details of individual bits , and default values are given here. control register 1 reg 0 x 0001 default value 0x001a msb lsb dl_ filt rd ovr rd gain rd off rd stat 0 sync flen3 flen2 flen1 flen0 byp f3 1 dec2 dec1 dec0 table 15. bit mnemonic description 15 dl_ filt 1 download filter. before downloading a user - defined filter, this bit must be set. the filter length bits must also be set at this time. the write operatio ns that follow are interpreted as the user coef ficients for the fir filter until all the coefficients and the checksum have been written. 14 rd ovr 1 , 2 read overrange. if this bit has been set, the next read operation outputs the contents of the overrange threshold register i ns tead of a conversion result. 13 rd gain 1 , 2 read gain. if this bit has been set, the next read operation outputs the contents of the digital gain register. 12 rd off 1 , 2 read offset. if this bit has been set, the next read operation outputs the contents of the digital offset register . 11 rd stat 1 , 2 read status. if this bit has been se t, the next read operation outputs the contents of the status register. 10 0 0 must be written to this bit. 9 sync 1 synchronize. setting this bit initiates a n internal synchroni z ation routine. setting this bit simultaneously on multiple devices synchronizes all filters. 8 - 5 flen3:0 filter length bits. these bits must be set when the dl fi lt bit is set and before a user - defined filter is downloaded. 4 byp f3 bypass filter 3. if this bit is 0, filter 3 ( p rogr ammable fir) is bypassed. 3 1 1 must be written to this bit. 2-0 dec2:0 decimation rate. these bits set the decimation rate of filter 2. all 0s implies that the filter is bypassed. a value of 1 corresponds to 2 decimation, a value of 2 corresponds to 4 decimation , and so on up to the maximum value of 5, corresponding to 32 decimation. 1 bit 15 to bit 9 are all self clearing bits. 2 only one of the bits from bit 14 to bit 11 can be set in any write operation because it determines the contents of the next r ead operation. control register 2 address 0 x 0002 default value 0x009b msb lsb 0 0 0 0 0 0 0 0 0 0 cdiv 0 pd lpwr 1 d1pd table 16. bit mnemonic description 5 cdiv clock divider bit. this sets the divide ratio of the mclk signal to produce the internal iclk. setting cdiv = 0 divides the mclk by 2. if cdiv = 1 , then the iclk frequency is equal to the mclk. 3 pd power down. setting this bit powers down the ad7762 , reducing the power co ns umption to 6.35 mw. 2 lpwr low power. if this bit is set, the ad7762 is operating in a low power mode. the power co ns umption is reduced for a 6 db reduction in noise performance. 1 1 write 1 to this bit. 0 d1pd differential amplifier power down. setting this bit powers down the on - chip differential amplifie r.
ad7762 data sheet rev. a | page 24 of 28 status register (read only) msb lsb part 1 part 0 die 2 die 1 die 0 dvalid lpwr ovr dl ok filter ok u filter byp f3 1 dec2 dec1 dec0 table 17. bit mnemonic comment 15, 14 part1:0 part number. these bits are constant for the ad7762. 13 to 11 die2:0 die number. these bits reflect the current ad7762 die number for identification purposes within a system. 10 dvalid data valid. this bit corresponds to the dvalid bit in the status word output in th e second 16-bit read operation. 9 lpwr low power. if the ad7762 is operating in low power mode, this bit is set to 1. 8 ovr if the current analog input exceeds the cu rrent overrange threshol d, this bit is set. 7 dl ok when downloading a user filter to the ad7762 , a checksum is generated. this checksum is compared to the one downloaded following the coefficients. if these checksums agree, this bit is set. 6 filter ok when a user-defined filter is in use, a checksum is genera ted when the filter coefficients pass through the filter. this generated checksum is compared to the one downloaded. if they match, this bit is set. 5 u filter if a user-defined filter is in use, this bit is set. 4 byp f3 bypass filter 3. if filter 3 is bypassed by setting the relevant bit in control register 1, this bit is also set. 3 1 this bit is always set. 2-0 dec2:0 decimation rate. these correspond to the bits set in control register 1. offset registeraddress 0x0003 non-bitmapped, default value 0x0000 the offset register uses twos complement notation and is scal ed such that 0x7fff (maximum positive value) and 0x8000 (maximum negative value) correspond to an offset of +0.78125% and ?0.78125%, respectively. offset correction is applied after any gain c orrection. using the default gain value of 1.25 and assuming a reference voltage of 4.096 v, the offset correction range is approximately 25 mv. gain registeraddress 0x0004 non-bitmapped, default value 0xa000 the gain register is scaled such that 0x8000 corresponds to a ga in of 1.0. the default value of this register is 1.25 (0xa000). this gives a full-scale digital output when the input is at 80% of v ref . this ties in with the maximum analog input range of 80% of v ref p-p. overrange registeraddress 0x0005 non-bitmapped, default value 0xcccc the overrange register value is compared with the output of the first decimation filter to obtain an overload indication with m inimum propagation delay. this is prior to any gain scaling or offset adjustment. the default value is 0xcccc which corresponds to 80% of v ref (the maximum permitted analog input voltage). assuming v ref = 4.096 v, the bit is then set when the input voltage exceeds approximately 6.55 v p-p differential. note that the overrange bit is also set immediately if the analog input voltage exceeds 100% of v ref for more than four consecutive samples at the modulator rate.
data sheet ad7762 rev. a | page 25 of 28 outline dime ns io ns compliant t o jedec s t andards ms-026-acd-hd 10-07-20 1 1-b 49 64 1 17 16 32 33 48 49 64 17 1 16 32 33 48 0.50 bsc lead pitch 7.50 bsc sq 12.20 12.00 sq 1 1.80 10.20 10.00 sq 9.80 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 7 3.5 0 0.15 0.05 0.08 coplanarity view a rotated 90 ccw 1.05 1.00 0.95 0.20 0.09 view a top view (pins down) pin 1 1.20 max se a ting plane 0.75 0.60 0.45 1.00 ref 0.27 0.22 0.17 bottom view (pins up) exposed pad figure 33 . 64 - lead thin quad flat pack age, exposed pad [tqfp _ep ] (sv - 64- 4 ) dime ns io ns shown in millimeters ordering guide model 1 temperature range package description package option ad 7762 bsvz ? 40c to +85c 64 - lead thin quad flat pack age , exposed pad (tqfp_ep) sv - 64 - 4 ad7762 bsvz - reel ? 40c to +85c 64- lead thin quad flat package, exposed pad ( tqfp_ep ) sv -64-4 eval - ad7762e b evaluation board 1 z = rohs compliant part.
ad7762 data sheet rev. a | page 26 of 28 notes
data sheet ad7762 rev. a | page 27 of 28 notes
ad7762 data sheet rev. a | page 28 of 28 notes ? 2005 C 2014 analog devices, inc. all rights reserv ed. trademarks and registered trademarks are the property of their respective owners. d05477 C0C 1/14(a)

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